工作內容:
-Familiar with Lattice architecture and good relationship with vendor -Familiar with Intel Whitley / Eagle Stream or AMD Genoa power on sequence control -Familiar with DCSCM topology design, DCSCM 2.0 will be plus -Familiar with I2C Mux, I/O Expander, SPI Mux, Hot-plug control… module design coding -Familiar with Verilog, C/C++ -Experience in PER/ROT solution design coding -Experience in Altera architecture